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gh_timer_8254_081608
- Timer 8254 Verilog source code
a8254
- 自己编写的8254计数器/计时器,实现了所有的6种模式,和大家一起分享。-I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
clock
- 描述了24小时计时的数字钟,同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
ApbTimer
- PowerFull Apb Timer Controller
iul
- 8.1 可编程并行接口芯片8255A 8.2 可编程定时器/计数器芯片8253/8254 8.3 串行通信及可编程串行接口芯片8251A 8.4 模/数(A/D)与数模(D/A)转换技术 及其接口 -8.1 programmable parallel interface chip 8255A8.2 programmable timer/counter chip 8253/82548.3 serial communications and programmable seri
Timer
- 基于vhdl的电子时钟,其中包括六进制计数器和十进制计数器。-VHDL-based electronic clock, including six hexadecimal decimal counters and counters.
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验,包括:基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ,这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写,有实验板和没有实验板的都可以用来学习。 其次还包括: FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档,很好用的文档,您下了相信不会后悔!-
Timer
- 麦克风阵列的TLS自适应波束形成算法仿真,麦克间距和输入信号带宽可调,通过调整参数达到需要的输出-TLS microphone array adaptive beamforming algorithm simulation, Mike spacing and input signal bandwidth is adjustable by adjusting the parameters to achieve the required output
stopwatch
- VHDL语言设计的秒表,实现计时功能,实现报时功能,并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
timer
- 基于硬件描述性语言vhdl的定时器timer的设计-timer
watch_dog_rtl_source
- Watchdog timer verilog RTL code
counter
- 用VHDL语言实现的计时器,最大计时为24小时,计时精度为1ms,设有复位和暂停功能,使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
timer
- 基于VHDL语言,实现时钟功能,显示时间从00:00:00到23:59:59,并将其输出信号转换为数码管信号-Based on the VHDL language, to achieve the clock function, display time from 00:00:00 to 23:59:59, and the output signal is converted to digital control signals
timer
- 这是一个基于FPGA设计的24时多功能数字钟,具有正常星期、时、分、秒计时,动态显示,保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, t
a_vhdl_8253_timer_latest.tar
- 一个用VHDL语言编写的8254定时器。具有一个同步处理器接口比异步的INTEL8254要好-A VHDL 8254 timer,uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.
DigitalClock
- 基于FPGA的数字电子钟设计,系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时,显示满刻度为23时59分59秒,另外有校时、校分和整点报时功能,并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency modul
shuzimiaobiaoVHDL
- 数字秒表的VHDL语言实现,由于系统定时器8253每秒中断18.2次,利用INT 1AH/00H取得中断次数(DX),得到54.945ms的定时单位。 -Digital stopwatch the VHDL language, because the system timer interrupt 18.2 times per second, 8253, made use of INT 1AH/00H interrupt number (DX), by 54.945ms timing uni
dip
- 计时器与出租车计价器源代码,编写语言为VHDL-Timer with the taxi meter source code, written language VHDL
7
- 调用总共四个计数器(两个六进制,两个十进制,六进制计数器可由实验五的程序做简单修改而成)串起来构成异步计数器,计数器的值,通过实验九串行扫描输出。用1Hz连续脉冲作为输入,这样就构成一个简单的1h计时器。带一个清零端。 输入:连续脉冲,逻辑开关;输出:七段LED。 -Called a total of four counters (two six-band, two decimal, hexadecimal counter by six experimental procedure
pwm_timer
- PWM和Timer的FPGA实现,文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.